The present invention relates generally to a memory module comprising a plurality of memory devices mounted on a single substrate. More particularly, it pertains to a memory module having a register (registered memory module) as well as to a memory module having a buffer (buffered memory module).
A registered memory module is a specific type of memory module which has a command and address (C/A) register commonly used by multiple memory devices mounted on a substrate. The C/A register latches (temporarily stores) a command signal or an address signal sent to the memory module and outputs the latched (temporarily stored) command and address signals as internal signals to relevant memory devices.
Generally, a personal computer employs more than one memory device on which multiple memory devices are mounted. Therefore, if C/A signals are directly to be supplied from a central processing unit (CPU) or a chip set (memory controller) to all the memory devices, it would be necessary to drive large capacitive loads for transmitting these C/A signals. In this situation, a C/A register is provided on each memory module to decrease the capacitive loads. In this arrangement, the memory devices mounted on one memory module are driven by the C/A register mounted on the same memory module and, when viewed from the CPU or the chip set, the C/A register is the only load mounted on the memory module.
Various proposals have conventionally been made in connection with the topology of a bus connecting the C/A register and multiple memory devices. Known examples of the topology of this bus (hereinafter referred to as the internal C/A bus) include a topology having a single-layer layout and a topology having a two-layer layout, the two types of topologies being hereinafter referred to as the single T-branch topology and as the dual T-branch topology, respectively, in this Specification. One example of the dual T-branch topology is introduced in technical information titled xe2x80x9cDDR SDRAM Registered DIMM Design Specificationxe2x80x94Revision 1.0xe2x80x9d available at the Web site http://www.chips.ibm.com/products/memory. One advantage of the dual T-branch topology is that it makes it possible to reduce the difference in the amounts of delays in signal transmission from the C/A register to individual devices compared to the single T-branch topology particularly when a large number of devices are mounted on the memory module.
There is a strong need in the memory device industry for improvements in data transfer rate in recent years, and this makes it necessary to increase the frequency of command and address signals.
A previously known technique for achieving high-frequency operation is to terminate bus lines. This technique has a drawback, however, in that it leads to an increase in power consumption.
It is an object of the invention to provide a registered memory module which employs a dual T-branch topology based on an unterminated bus structure to provide an improved high-frequency operating capability.
In an attempt to overcome the aforementioned problems of the related art, the inventor of this invention carried out operational tests of currently available memory module products using a technique of performance simulation. Specifically, currently available memory module products incorporating a C/A register designed to operate at 67 MHz were tested at 150 MHz by simulation. Even when the physical size of a metal-oxide-semiconductor (MOS) transistor serving as an output transistor of the C/A register was varied in various ways, it was impossible to obtain satisfactory waveforms if bus lines are not terminated. It is generally known that bus lines should be terminated to obtain satisfactory waveforms. This termination technique, however, poses another problem that it causes an increase in power consumption. Thus, the inventor has studied a method of obtaining satisfactory waveforms without using terminal resistors.
Generally, when executing this kind of waveform simulation test, waveforms are examined by substituting an impedance corresponding to a waveform input of a particular topology for a resistor. The substitute impedance used in such a test is the impedance at a point of the topology corresponding to the output transistor of the C/A register in the case of a registered memory module, for example. More particularly, it is the output impedance of the C/A register viewed from an input terminal of a C/A bus. To investigate the feasibility of various topologies, simulation tests were performed assuming the output impedance produced by the aforementioned arrangement of the resistor. As a result of the tests, the inventor succeeded in obtaining satisfactory waveforms using an unterminated dual T-branch topology rather than a single T-branch topology even when the frequency was increased up to 150 MHz.
The inventor further carried out additional simulation tests by substituting the output impedance simulated by the resistor for a MOS transistor. It was however impossible to obtain satisfactory waveforms with this arrangement.
After a careful investigation, the inventor postulated that a major cause of the aforementioned problems should exist in the fact that the transistor did not have a constant on-state resistance, that is, the transistor was not operated in its linear region. Specifically, assuming that the cause of the problems was inconstancy of the output impedance of the C/A register viewed from the input terminal of its C/A bus, the inventor presumed that the problems could be solved if the C/A bus was operated under conditions in which the output impedance of the C/A register was kept substantially constant. Based on this assumption, a resistor was connected to an output terminal of an output MOS transistor in series therewith to make the output impedance substantially constant and reexecuted a simulation test. It was however impossible again to obtain successful results.
A further investigation was carried out, from which the inventor has discovered that the gradient of the leading and trailing edges of an output pulse waveform, or the rise time (tR) and fall time (tF) of the pulse waveform, are closely related to achieving satisfactory waveforms.
The inventor of the invention has further examined the behavior of memory modules and discovered also that the output pulse waveform is related to the number of memory devices mounted on the modules.
Based on the aforementioned investigations and the results thereof, the invention provides the following memory modules as means for overcoming the problems of the related art.
A first memory module of the invention comprises a command/address register device for generating an internal signal according to an external command/address signal, the command/address register device having an output transistor, a plurality of memory devices divided into first and second groups, wiring interconnecting the command/address register device and the memory devices, and a substrate on which the command/address register device and the multiple memory devices are mounted. In this memory module, the wiring includes a first wiring section extending from the command/address register device to a first branch point, a second wiring section extending from the first branch point to a second branch point, a third wiring section extending from the first branch point to a third branch point, a fourth wiring section which branches out from the second branch point and extends up to the memory devices of the first group, and a fifth wiring section which branches out from the third branch point and extends up to the memory devices of the second group, and the command/address register device includes an impedance adjuster for adjusting the output impedance of the command/address register device viewed from a junction point between the command/address register device and the first wiring section in such a manner that the output impedance of the command/address register device becomes substantially constant within an operating voltage range of the internal signal, and a rise time/fall time adjuster for adjusting rise time and fall time of the internal signal to specific values.
A second memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that neither of the multiple memory devices nor the wiring is terminated.
A third memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the command/address register device is a command/address register including the aforementioned output transistor and having a register output terminal, the command/address register device including a resistor connected to the register output terminal, the resistor serving as the impedance adjuster.
A fourth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the command/address register device is a command/address register incorporating a resistor serving as the impedance adjuster.
A fifth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the impedance adjuster includes first and second resistors, and the command/address register device is a command/address register having a register output terminal and includes the second resistor connected to the register output terminal, the command/address register including the output transistor and the first resistor which is connected between an output terminal of the output transistor and the register output terminal.
A sixth memory module of the invention, which is a variation of the aforementioned fifth memory module, is characterized in that the resistance of the first resistor is set to a value which is smallest in consideration of potentially selected numbers of the memory devices, and the resistance of the second resistor is set to a value to be added to the resistance of the first resistor for properly adjusting the output impedance of the command/address register device.
A seventh memory module of the invention, which may be a variation of any one of the aforementioned first to sixth memory modules, is characterized in that the Command/address register incorporates a capacitor serving as the rise time/fall time adjuster.
An eighth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the impedance adjuster adjusts the output impedance of the command/address register device according to the number of the memory devices mounted on the substrate.
A ninth memory module of the invention, which may be a variation of either of the aforementioned third to fourth memory modules, is characterized in that the resistance of the resistor is larger than the on-state resistance of the output transistor.
A tenth memory module of the invention, which is a variation of the aforementioned fifth memory module, is characterized in that the combined resistance of the first and second resistors is larger than the on-state resistance of the output transistor.
An eleventh memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the specific values of the rise time and the fall time remain constant regardless of the potentially selected numbers of the memory devices.
A twelfth memory module of the invention, which is a variation of the aforementioned eleventh memory module, is characterized in that the frequency of the internal signal is at least 100 MHz.
A thirteenth memory module of the invention, which is a variation of the aforementioned twelfth memory module, is characterized in that the rise time and the fall time fall within a range of 0.9 ns to 2.0 ns.
A fourteenth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the number of the memory devices of the first group is larger than the number of the memory devices of the second group by a specific number and all the memory devices have substantially the same input capacitance with one another, the memory module further comprising the aforementioned specific number of dummy capacitors connected to the fifth wiring section together with the memory devices of the second group, each of the dummy capacitors having substantially the same input capacitance as the individual memory devices, wherein the combined impedance of the memory devices of the first group viewed from the second branch point is equal to the combined impedance of the memory devices of the second group and the dummy capacitors viewed from the third branch point.
A fifteenth memory module of the invention, which is a variation of the aforementioned fourteenth memory module, is characterized in that the second and third wiring sections have equal line impedance and the fourth and fifth wiring sections have equal line impedance.
A sixteenth memory module of the invention, which is a variation of the aforementioned fourteenth memory module, is characterized in that the fourth wiring section forms a local topology in which nodes of the memory devices of the first group are arranged symmetrically with respect to a first imaginary line passing through the second branch point, and the fifth wiring section forms a local topology in which nodes of the memory devices of the second group and the aforementioned specific number of the dummy capacitors are arranged symmetrically with respect to a second imaginary line passing through the third branch point,
A seventeenth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the number of the memory devices of the first group is larger than the number of the memory devices of the second group by a specific number and all the memory devices have substantially the same input capacitance with one another, and line lengths of the second to fifth wiring sections are determined in such a manner that the combined impedance of the memory devices of the first group viewed from the first branch point is equal to the combined impedance of the memory devices of the second group viewed from the first branch point.
An eighteenth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the number of the memory devices of the first group is 8 or 10 while the number of the memory devices of the second group is 8, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while the output impedance of the command/address register device is 20 ohms xc2x120%.
A nineteenth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the number of the memory devices of the first group is 4 or 5 while the number of the memory devices of the second group is 4, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while the output impedance of the command/address register device is 25 ohms xc2x120%.
A twentieth memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the number of the memory devices of the first group is 2 or 3 while the number of the memory devices of the second group is 2, and the line impedance of the first to fifth wiring sections substantially falls within a range of 50 to 65 ohms while the output impedance of the command/address register device is 30 ohms xc2x120%.
A twenty-first memory module of the invention, which is a variation of the aforementioned first memory module, is characterized in that the memory module comprises a buffer device including the impedance adjuster and the rise time/fall time adjuster instead of the command/address register device.
As would be understood from the foregoing, the invention provides a registered or buffered memory module employing the dual T-branch topology based on the unterminated bus structure having a high-frequency operating capability with the provision of an impedance adjuster for adjusting the output impedance of a C/A register or buffer viewed from an input terminal an internal C/A bus and a rise time/fall time adjuster for adjusting rise time and fall time of an internal signal output from the C/A register or buffer to the internal C/A bus.
These and other objects, features and advantages of the invention will become more apparent upon reading the following detailed description in conjunction with the accompanying drawings.
FIG. 1 is a general configuration diagram of a memory module according to a first embodiment of the invention;
FIG. 2 is a simplified equivalent circuit diagram of each via hole shown in FIG. 1;
FIG. 3 is a simplified equivalent circuit diagram of an input portion of each DRAM device shown in FIG. 1;
FIG. 4 is a diagram showing the general circuit configuration of a C/A register shown in FIG. 1;
FIG. 5 is a diagram for explaining the output impedance of the C/A register viewed from an input terminal of a first wiring section particularly when an n-channel MOS (nMOS) transistor of a complementary MOS (CMOS) inverter constituting an output stage of the C/A register is in an ON state;
FIG. 6 is a diagram for explaining the output impedance of the C/A register viewed from the input terminal of the first wiring section particularly when a p-channel MOS (PMOS) transistor of the CMOS inverter constituting the output stage of the C/A register is in an ON state;
FIG. 7 is a general configuration diagram of a memory module according to a second embodiment of the invention;
FIG. 8 is a general configuration diagram of a memory module according to a third embodiment of the invention;
FIG. 9 is a diagram showing the relationship between tR/tF adjustment and waveforms; and
FIG. 10 is a general configuration diagram of a memory module according to a fourth embodiment of the invention.